Certified Professional Diploma in Chip Designing
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Certified Professional Diploma in Chip Designing
COURSE CONTENTS & OBJECTIVES DISPLAYED. HOWEVER YOUR ACCESS TO OUR LMS WILL BE PROVIDED AFTER ADMISSION CONFIRMATION
Description
With technological advances that allow us to integrate complete multi-processor systems on a single die, Systems-on-Chip (SoCs) are at the core of most embedded computing and consumer devices, such as cell phones, media players, and automotive, aerospace, or medical electronics. This course will provide an understanding of the concepts, issues, and process of designing highly integrated SoCs following systematic hardware/software co-design & co-verification principles. Specifically, the class project involves taking public domain C++ code for a machine learning-based visual object recognition application utilizing a deep/convolutional neural network (DNN/CNN) and mapping it to an ARM-based virtual and FPGA prototyping platform using state-of-the-art synthesis and verification tools and design flows.
Objective
- This course is designed for students to learn and be able to:
- Analyze the functional and non-functional performance of the system early in the design process to support design decisions.
- Analyze hardware/software trade-offs, algorithms, and architectures to optimize the system based on requirements and implementation constraints.
- Analyze trade-offs and explore architecture and micro-architecture design spaces to develop and synthesize custom hardware accelerators
- Understand hardware, software, and interface synthesis.
- Understand issues in interface design.
- Use co-simulation to validate system functionality.
- Describe examples of applications and systems developed using a co-design approach.
- Appreciate issues in system-on-chip design associated with co-design, such as intellectual property, reuse, and verification.
Module 1
Hardware/software co-design
partitioning, real-time scheduling, hardware acceleration;
Virtual prototyping: electronic system-level languages and hardware/software co-simulation
Module 2
High-level synthesis
allocation, scheduling, and binding algorithms for C-to-RTL synthesis;
SoC integration: SoC communication architectures
Assignments
Module 3
IP interfacing
verification and test
FPGA prototyping of hardware/software systems.
Assignments
Exam
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